The fundamental task of yield analysis is to determine the root cause of yield loss so that the consultant, factory engineer and/or designer can take action to mitigate the yield loss mechanism(s). The fundamental challenge is to connect the yield loss, as manifested in failure bit map (FBM) failures or die sort fail bins, as presented by e-test data, to its root cause. Typically, the source of the bin failures from the test data is unknown, but without this information a course of action cannot be taken to resolve the issue. Standard techniques for finding yield loss mechanisms include correlation analysis of yield vs. inline data, e-test data, defect, or wafer process history data. However, straightforward correlation analysis is hampered by the fact that in the manufacture of IC's, hundreds of process steps involving many pieces of associated equipment are employed, anyone of which may contribute to yield loss. Because of the superposition of yield impacting signals, correlation analysis signals may be weak or obscured because multiple failure modes may be present in a given population of wafers.
Generally, yield loss in semiconductor processing may be characterized as being composed of two components; systematic yield loss and random yield loss. This systematic yield loss may occur due to poor processing conditions or centering at a given process step, or perhaps the yield loss may be associated with a design marginality or flaw. Random yield loss tends to be associated with normal operating conditions where the background levels of defectivity from the fab ambient environment and/or ambient within tools contribute to defects on the wafer. Partitioning methods attempt to discern the random yield loss from the systematic yield loss so that subsequent investigation into root cause(s) can address each issue as deemed necessary. One such method uses a wafer tiling algorithm whereby die are aggregated into groups of die of varying size such that the slope of the logarithm of group yields vs. group size is an estimate of the random defectivity (Do) assuming Poisson statistics, and the y-intercept is an estimate of the systematic yield (Ys) (Segal et al., 2000). In this latter approach, one is able to get an estimate of Ys for a given wafer(s), but it is not readily possible to group wafers with similar Ys values as belonging to the same root cause group or cluster of wafers because no spatial distribution information is maintained. In other words, different root causes may have similar Ys values. Other methods do not rely on the test data but utilize test chips that contain representative attributes that can define the systematic yield values as they are related to an IC product.
A first method of identifying yield loss and drill down analysis (identifying the fundamental root cause of failure) is disclosed in U.S. Pat. No. 6,393,602 by Atchison et al., which discloses a yield management method by which clustering is done in a similar manner as prescribed by Segal et al., “Reducing baseline defect density through modeling random defect limited yield”, MicroMagazine, January 2000. They employ a negative binomial statistic to estimate the systematic and defect limited yield. In this case, a clustering factor is estimated but this clustering factor is an aggregate across the wafer or wafers. In other words, assuming a fairly symmetric wafer, this method would not discriminate between N chips failing in the upper left corner versus N chips failing in the lower right corner, but the physical mechanisms for these yield losses are likely very different. Further, Atchison et al. go on to disclose the use of spatial analysis but only in a straightforward and rudimentary manner whereby wafer region yields are simply plotted in 2-D projections for visual review.
U.S. Pat. No. 6,470,229 by Wang et al, discloses a comprehensive yield management system and method using data pre-processing to remove bad data and data mining techniques to generate a decision tree for an automated analysis system. The data mining system is used to build a decision tree to find relationships between the response variable and the predictor variable(s) to find the best decision-split based on each predictor. In this way, the response variable, typically yield, may be related to one or more predictor variables. These types of generalized data mining techniques, while in principle are very elegant and attractive, in practice fall short of expectations due to large amounts of noise in the system.
In the semiconductor manufacturing process the process wafers are subject to random and non-random spatial defect sources/root causes. Some clustering algorithms attempt to discern between the random and non-random defect components by assigning the non-random defect pattern(s) to a given cluster. Clustering has been applied to optical defect inspection data to determine if a given defect is actually part of a group of other defects, e.g., associated with a scratch. Other clustering algorithms may not specifically attempt to discern between random and non-random responses but rather simply group wafers with similar patterns inclusive of random and non-random responses. This latter approach is more generally used when looking at patterns of bin data. Differentiating between different clusters is an additional burden that an algorithm must properly perform to be useful so as to distinguish different patterns and hence root causes.
To accomplish this separation, a clustering metric is applied and a clustering criteria and/or threshold are set. Some metric of difference criteria is set to provide a threshold of association. Hansen and James (Bell Labs Technical Journal, 1997) discuss an approach where they applied smoothing to spatial pass/fail bin die sort data based on a user selected smoothing threshold. They then test the resulting wafer map for spatial randomness based on joint count statistics. If the wafer map fails the spatial randomness test it is compared with other wafers that have failed the same test using a hierarchical clustering method using the “thresholded maps”. The association of wafers in clusters suggests that the wafers in the group may likely have similar root causes for their die failures. In this way, clustering of wafers may aid in the diagnosis of yield limiting issues in the fabrication process. The “thresholded maps” constitute a library of known wafer patterns that are correlated against process wafers coming from the production line. In this way, wafers can be classified as belonging to a certain group of previously defined patterns. The problem with this approach is that it is only strictly valid for a given process and product layout which is relatively mature because the catalog or library of patterns is not necessarily static, especially as technology nodes change and as new process steps and materials are introduced (See “International Technology Roadmap for Semiconductors,” 2001 Edition. Semiconductor Industry Association, 2001.) Also, this technique has been applied to the overall fail bin vs. pass bin case but does not seem readily amenable to exploring the generalized bin failure case as is the case for the invention disclosed herein. Other software applications (e.g. S-Wafers) essentially divide all wafers up and the engineer has to visually group the wafers with similar patterns together.